1. Field of the Invention
The present invention relates to a control apparatus and control method using direct memory access.
2. Description of the Related Art
Drive mechanisms used in the latest electronic devices require extremely fast, accurate operation. One control method known to be able to satisfy these requirements uses direct memory access (DMA). DMA enables data to be sent by a dedicated hardware circuit directly from memory to the drive mechanism controller instead of passing first through the CPU. Because DMA allows the drive mechanism to be controlled without calling the CPU, DMA is also compatible with high speed operation of the drive mechanism.
Japanese Patent Laid-Open Publication (kokai) 2001-327191 teaches a control apparatus that applies DMA to control a printer drive mechanism. This control apparatus has a timing data table that stores timing data defining the timing at which control changes, and a control data table that stores control data used each time control changes. After a CPU drive start request is asserted, a first DMA channel sends timing data from the timing data table to the timer, and each time the timer times out an activate signal is sent to a second DMA channel. Each time this second DMA channel receives an activate signal, it sequentially supplies control data stored in the control data table to the drive mechanism control unit. Once the CPU issues the drive start request, this configuration thus enables controlling the drive mechanism according to predefined timing data and control data without involving the CPU.
Furthermore, the second DMA channel has a plurality of DMA channels, each corresponding to a respective one of a plurality control data types. When DMA transfer of the first control data is completed by activation of the first DMA channel, the next DMA channel is activated to pass the second control data, and so forth. DMA control can thus be used to operate a drive mechanism based on plural control data types.
More specifically, the above-cited control apparatus is configured to link operation of plural DMA channels in a control chain, thereby enabling controlling a drive mechanism using plural types of control data without involving the CPU.
As described above, when an activate signal is applied to the second DMA channel in the conventional control apparatus described above, the plural DMA channels in the second DMA channels are automatically activated in sequence. This makes it difficult to achieve complicated control processes, such as supplying control data with different timing to plural controlled objects, because the activation timing of these plural DMA channels cannot be separately controlled.